Although there are numerous forms of buffer circuits which are capable of buffering input voltages having TTL voltage levels to provide output voltages having MOS voltage levels, such buffer circuits typically consume power when at least one of the MOS voltage levels is provided. A well known buffer circuit utilizes an N-channel depletion load transistor connected in series with an N-channel transistor having its control electrode connected to an input voltage. The load transistor functions as a constant current source. The N-channel transistor is fabricated to have a switchpoint threshold voltage which is equal to a mid-range value of the TTL trip point voltage. Disadvantages with this buffer circuit include the fact that when the input voltage makes the N-channel transistor conductive, current flows through both the load transistor and the N-channel transistor thereby dissipating a large amount of power. However, because both transistors are of the same conductivity type and have near identical processing steps, the buffer circuit exhibits a substantially constant switchpoint voltage with respect to processing variations and temperature. On the other hand, a conventional CMOS inverter circuit comprising a P-channel transistor connected in series to an N-channel transistor does not provide a constant switchpoint with respect to process and temperature due to the processing differences between the transistors of opposite conductivity. To overcome the power dissipation problem of an all N-channel buffer circuit, others have utilized an additional power down transistor of the same conductivity type to separately power up and power down the circuit. Such a circuit is taught by U.S. Pat. No. 4,384,220 by Segawa et al. However, such circuits continue to dissipate power for at least one level of the input voltage. Also, additional control voltages are required.